
-- VHDL Instantiation Created from source file Processor.vhd -- 11:44:18 03/04/2012
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT Processor
	PORT(
		clk_i : IN std_logic;
		clr_i : IN std_logic;
		instr_ack_i : IN std_logic;
		instr_word_i : IN std_logic_vector(17 downto 0);
		data_ack_i : IN std_logic;
		data_word_i : IN std_logic_vector(7 downto 0);
		int_req : IN std_logic;
		port_ack_i : IN std_logic;
		port_word_i : IN std_logic_vector(7 downto 0);          
		instr_cyc_o : OUT std_logic;
		instr_stb_o : OUT std_logic;
		instr_addr_o : OUT std_logic_vector(9 downto 0);
		data_cyc_o : OUT std_logic;
		data_stb_o : OUT std_logic;
		data_we_o : OUT std_logic;
		data_addr_o : OUT std_logic_vector(7 downto 0);
		data_word_o : OUT std_logic_vector(7 downto 0);
		int_ack : OUT std_logic;
		port_cyc_o : OUT std_logic;
		port_stb_o : OUT std_logic;
		port_we_o : OUT std_logic;
		port_addr_o : OUT std_logic_vector(7 downto 0);
		port_word_o : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	Inst_Processor: Processor PORT MAP(
		clk_i => ,
		clr_i => ,
		instr_ack_i => ,
		instr_word_i => ,
		data_ack_i => ,
		data_word_i => ,
		int_req => ,
		port_ack_i => ,
		port_word_i => ,
		instr_cyc_o => ,
		instr_stb_o => ,
		instr_addr_o => ,
		data_cyc_o => ,
		data_stb_o => ,
		data_we_o => ,
		data_addr_o => ,
		data_word_o => ,
		int_ack => ,
		port_cyc_o => ,
		port_stb_o => ,
		port_we_o => ,
		port_addr_o => ,
		port_word_o => 
	);


